Integrated circuits comprise a plurality of devices that are formed in one surface of a semiconductor substrate. A typical integrated circuit has a number of bond pads on the periphery of the die and surrounding active devices of the integrated circuit. The bond pads are connected through an interconnect layer to one or more terminals of the devices in the integrated circuit. The interconnect layer includes a dielectric material that insulates interconnecting conductors from each other. The conductors extend from device terminals to the bond pads. The semiconductor die is mounted on a central platform of a lead frame that has a plurality of fingers radially extending from a peripheral metal frame towards the central platform. Very thin wire bonds, typically of gold or gold and aluminum alloy, connect the bond pads of the integrated circuit to the lead fingers on the lead frame. Then the integrated circuit is encapsulated in plastic or ceramic, the frame members are trimmed, and the external leads are bent into their appropriate form. The external leads are connected to other integrated circuits, power supplies, or other electronic components.
Bond wires are a source of parasitic inductance. That inductance can be particularly troublesome at high frequencies. In order to eliminate bond wire parasitic inductance, others have proposed using bump type connectors for contacting the external integrated circuit contacts, i.e. bond pads.
Integrated circuits generate heat during operation. Accordingly, removal of that heat is important in order to keep the integrated circuits from failing. Others have used heat sinks and special packages for removing heat from the integrated circuit die. Accordingly, it is desirable to provide a method and apparatus that quickly removes heat from the integrated circuit.
Still another problem with integrated circuits is the thickness of epitaxial layers. This problem is particularly acute in power devices, such as quasivertical DMOS devices (QVDMOS). Those devices have a relatively large buried layer that forms the drain contact for the QVDMOS device. The QVDMOS device also has a large heavily doped vertical drain diffusion for contacting the buried horizontal layer. In the QVDMOS device, source regions are separated by a common gate. In operation, the gate vertically couples the source to the buried layer drain diffusion. The buried layer drain diffusion is itself coupled to the surface via the surface drain diffusion.
Such QVDMOS devices have two disadvantages. For one, in order to sufficiently space the source regions from the buried layer region the heavily doped buried layer requires a substantially thick epitaxial layer. The epitaxial region is often required to be in excess of 20 microns in order to provide sufficient spacing between the source and buried layer. Growing epitaxial layers above 20 microns is both difficult and time consuming. The epitaxial process requires more time to grow thicker layers than to grow thin layers. Moreover, thick layers are notorious for having stacking faults and other defects. The other disadvantage is the relatively large sinker diffusion that is required for making contact to the buried layer. Due to the thickness of the epitaxial region, the vertical drain diffusion to the buried layer expands laterally during formation. As such, substantial portions of the integrated circuit die are only used to establish contacts to a buried layer.
Others have proposed solutions to some of these problems by establishing conductive vias between the surface of a device layer and a buried layer. However, even with highly selective etching techniques, the size of such conductive vias is often equal to or greater than the extent of a lateral diffusion of the vertical drain diffusion. In addition, the fabrication and metallization of deep vias is extremely difficult.
In U.S. Pat. No. 4,889,832 there is shown a scheme for using conductive vias to interconnect multiple epitaxial layers of a device. That patent relies upon depositing multiple epitaxial layers to form stacks of transistors in the multiple epitaxial layers. The devices are not formed in the face of one device layer but rather are formed in multiple device layers stacked on top of one another. Others show techniques for exposing the backside surface of a device wafer for making contact to topside surface diffusions that extend from the backside surface. See, for example, U.S. Pat. No. 5,004,705, in particular FIGS. 10 and 11. Another example of using a conductive via to provide a backside contact is found in U.S. Pat. No. 5,424,245. However, the later patent does not thin the device wafer to expose either a buried layer contact or a diffusion made from the topside surface. It also does not address the problem of thick epitaxial layers in QVDMOS devices. Still other examples of patents that show processing techniques on the backside surface of a wafer opposite the topside surface that receives the diffusion are shown in U.S. Pat. Nos. 5,308,779; 4,892,842; and 3,991,599.
Accordingly, there has been a long felt need for devices that minimize or eliminate bond wire parasitic inductances, that rapidly remove heat from integrated circuits, and that minimize the area consumed by vertical diffusions to buried layers.